MODELLING BACKSCATTERING EFFECTS IN NANOSCALE CMOS TRANSISTORS USING DRIFT DIFFUSION SIMULATIONS WITH MASTER 4

Abstract

The effects of strain engineering and gate length optimization on the electrical performance of MOSFETs have been examined using Advanced Master 4 simulation software. A tensile strain of 1.5% was applied along both the "x" and "y" directions, with fixed boundary conditions at the source and drain, allowing for strain variation across the channel. All simulations were conducted at room temperature (300 K), to evaluate the influence of strain and channel length variation on electron mobility and overall device behavior. The results revealed a significant improvement in electron mobility for strained devices, increasing from 3.40 X 10-24cm²/Vs in unstrained devices to 4.18 X 10-24 cm²/Vs in strained ones. Additionally, shortening the channel length from 25 nm to 10 nm enhanced both injection velocity and drive current, with strained devices achieving a higher injection velocity of 6.80 X 104 m/s compared to 6.30 X 104 m/s in unstrained devices. The I-V characteristics, on the other hand indicated a substantial increase in on-current for strained MOSFETs, demonstrating enhanced performance due to improved ballistic transport and reduced backscattering effects. Further analysis of the F-carrier distribution function showed sharper peaks in strained devices, signifying higher carrier concentrations and minimized scattering which is a crucial factor for achieving quasi-ballistic transport. Moreover, the simulations highlighted the impact of strain and gate length scaling on the conduction band structure, with strained devices consistently showing superior performance.